郑willy

程序：

module top;
integer ia[1:0],ib[1:0];
integer icin;
reg [1:0]a,b;
reg cin;
wire cout;
wire [1:0]sum;

and_behavioral add2(cout,sum,a,b,cin);

initial
begin
for (ia[0]=0; ia[0]<=1; ia[0] = ia[0]+1)
begin
a[0]= ia[0];
for (ia[1]=0; ia[1]<=1; ia[1] = ia[1]+ 1)
begin
a[1] = ia[1];
for (ib[0]=0; ib[0]<=1; ib[0] = ib[0]+1)
begin
b[0] = ib[0];
for (ib[1]=0; ib[1]<=1; ib[1] = ib[1]+ 1)
begin
b[1] = ib[1];
for (icin=0; icin<=1; icin = icin + 1)
begin
cin = icin;
#1 $display("a[0]=%d a[1]=%d b[0]=%d b[1]=%d sum[0]=%d sum[1]=%d cout=%d cin=%d ",a[0],a[1],b[0],b[1],sum[0],sum[1],cout,cin);
end
end
end
end
end
end
endmodule

module and_behavioral (cout,sum,a,b,cin);
output [1:0]sum;
output cout;
input [1:0] a,b;
input cin;
wire t;

add a1(t,sum[0],a[0],b[0],cin);
add a2(cout,sum[1],a[1],b[1],t);

endmodule

module add(cout,sum,a,b,cin);
input a,b,cin;
output cout,sum;
wire a,b,cin;
reg cout,sum;
always @(a or b or cin)
begin
cout = a&cin|a&b|b&cin;
sum = ~a&b&~cin|~cin&a&~b|a&b&cin|~a&~b&cin;
end
endmodule

module top;
wire A, B, Cin, E, F, G, cout, SUM;
system_clock #400 clock1(Cin);
system_clock #200 clock2(B);
system_clock #100 clock3(A);
and a1(E, A, B);
xor a2(F, A, B);
and a3(G, F, Cin);
or a4(cout,E, G);
xor a5(SUM, F, Cin);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>1000)$stop;
endmodule

module top;
integer ia,ib,ic;
reg a,b,cin;
wire cout,sum;
and_behavioral and1(cout,sum,a,b,cin);
initial
    begin
      for (ia=0; ia<=1; ia = ia+1)
        begin
          a = ia;
          for (ib=0; ib<=1; ib = ib + 1)
            begin
              b = ib;
  for (ic=0; ic<=1; ic = ic + 1)
  begin
  cin=ic;
              #1 $display("a=%d b=%d cin=%d cout=%d sum=%d",a,b,cin,cout,sum);
                        end
    end
     end
end
endmodule
module and_behavioral(cout,sum,a,b,cin);
input a,b,cin;
output cout,sum;
wire a,b,cin;
reg cout,sum;
always @(a or b or cin)
   begin
    cout = a&cin|a&b|b&cin;
    sum = ~a&b&~cin|~cin&a&~b|a&b&cin|~a&~b&cin;
   end
endmodule

module test_adder1;
reg a,b;
reg carry_in ;
wire sum;
wire carry_out;
adder1_behavorial A1(carry_out, sum, a, b, carry_in);
initial
begin
    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
   carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out != 0 | sum !== 1)
                $display(" 0+0+1=01 sum is WRONG!");
              else
                $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_out != 0 | sum !== 1)
               $display(" 0+1+0=01 sum is WRONG!");
              else
               $display(" 0+1+0=01 sum is RIGHT!");
   carry_in = 0; a = 1; b = 1;
    # 100 if ( carry_out != 1 | sum !== 0)
               $display(" 0+1+1=10 sum is WRONG!");
              else
               $display(" 0+1+1=10 sum is RIGHT!");
   carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 1)
               $display(" 1+0+0=01 sum is WRONG!");
              else
               $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_out != 1 | sum !== 0)
               $display(" 1+0+1=10 sum is WRONG!");
              else
               $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out != 1 | sum !== 0)
               $display(" 1+1+0=10 sum is WRONG!");
              else
               $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_out != 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");
    $finish;
end
endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);
input a, b, carry_in;
output carry_out, sum;
assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule